High-performance systems-on-a-chip (SoCs) using over 10 million gates have now become a reality.
ASIC/SoC designers now face the tremendous challenge of producing high-quality complex designs in
a short amount of time. To meet a new set of challenges unique to SoC designs, new tools and
methodologies are required. While design exploration must start at higher levels of abstraction to
improve productivity, shrinking circuit geometries require that difficult physical issues be
addressed from early in the design cycle.
For example, layout-based synthesis (physical synthesis) is becoming indispensable as a means
of enabling rapid timing closure. At the same time, to prevent quality problems from worsening,
Toshiba have improved the methodologies and tools to resolve signal integrity issues such as voltage drop and crosstalk.
Furthermore, we embrace industry-leading EDA tools aggressively. Toshiba offers design
environments built on and integrated into these tools. All of them are in keeping with our overriding commitment to providing you with
unsurpassed ASIC/SoC solutions. We believe that offering the best silicon capability is not enough and that it is equally important to
offer tools and methodologies so you can put our world-class silicon capability to work for you as smoothly as possible.
Design flow details
For more detailed information download the official
Toshiba SoC EDA Product Guide
(pdf 1619KB) or follow the links in the design flow overview below.
In case of any further questions, contact the
ASIC & Foundry team
Design Flow
System design results
(RTL)
Logical design
Design
• Logic Synthesis
• Test Synthesis
• Design planning
etc.
Verification
• Handover Verification
• Logic Simulation
• Timing Analysis
• Formal Verification
etc.
Logic design results
(Netlists, Timing constraints & IC Floorplan)
Physical design
Design
• Floorplanning
• Physical Synthesis
• Routing
• SI Prevention
• DFM
etc.
Verification
• DRC
• Crosstalk
• IR Drop
• Timing
• Yield
etc.
Physical layout results
(GDS)
RTL to Gates & Handoff
The RTL code is synthesized into gates using a logic synthesis tool.
The design is optimized to meet the timing constraints you set.
Design For Testability (DFT)
DFT structures such as boundary-scan and internal-scan circuitry are inserted to your logic design.
Then, ATPG is run to generate test patterns that make use of the DFT structures.
Timing Analysis
Timing analysis and verification are performed on the gate-level design.
This step allows you to generate timing constraints for physical layout.
Sign-Off Solutions
Toshiba offer Design Kits to support static
and simulation based Sign Off verification. High accuracy 3D extraction and delay calculation technology is used to guarantee sign off quality timing.
Test Solutions
IEEE std 1450 Standard Test Interface
Language STIL is used throughout the entire design & test process without any test data conversion.
Design Prototyping
An IC floorplan is created and its
physical feasibility in terms of die size, power, routing and timing is verified.
Physical Synthesis
Logic and timing optimization is combined
with placement and global routing to achieve a better timing accuracy and higher circuit speed.
Place & Route
Detailed routing and clock tree synthesis is performed on the previously optimized placement. By means of subsequent post-routing optimizations convergence of timing and signal integrity targets is reached.
SI Solutions
Signal integrity (e.g. crosstalk, IR drop) prevention,
analysis and repair is performed concurrently to the physical implementation.
DFM Solutions
"Design-for-Manu-
facture" aspects and solutions are considered from early in the design cycle.
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