Display Bridge and Hub components facilitate the link between application processors and displays by combination of a large variety of industry interface standards. Serial (MIPI® & MDDI®) and parallel host interfaces can output the content to displays with parrallel, serial (MIPI®) or LVDS connectors. In addtion multiple displays can be realized by MIPI® DSI hubs (1 DSI in, multiple DSI out).
Toshiba's Display Bridge/Hub has various display interfaces to facilitate design of feature-rich mobile equipment realizing superb picture quality.
Examples of Display Bridge Configurations
MDDI(R) VEGAMagiq FWVGA - WVGA - VGA Display Controller - TC358720/21/22/23XBG
VEGAMagiq is Toshiba’s MDDI (Mobile Display Digital Interface) LCD controller, optimized for mobile phones equipped with a high resolution LCD panel. Since the mobile industry trend is going to high-resolution and wide colour range displays in high-end clam-shell style phones, connections between base body and the display subsystem becomes more and more complex.
VEGAMagiq has a high-speed serial digital packet host interface that is compliant with VESA MDDI standard. This serial data interface supports throughputs of up-to 400Mbps by using two low-voltage differential signal pairs. It is compatible to systems that are using Qualcomm’s MSM™ baseband family. Due to the combination of LVDS technology with on-chip eDRAM memory buffer, VEGAMagiq supports VGA size main LCD panel and QCIF+ size sub LCD panel with low EMI emission and high reliability through the handset’s hinge.
An enhanced version for WVGA (864*480) is also available (VEGAMagiq-W) TC358722XBG.
Read more... (pdf 47KB)
MDDI® to DSI-Display Bridge / TC358760XBG
Features
- Support MDDI® 1.2 Direct refresh (60 fps) up to FWVGA
- LCD-I/F: MIPI® DSI 3lane
- Multiple display bridges:
MDDI®->DSI/DPI/DBI, DPI/DBI->DSI
- Resolution: Up to qHD, HXGA (DPI-to-DSI mode)
- Host interfaces: MDDI® 1.2 Type 1, DPI 24-bit , DBI-B 16-/18-bit
- LCD interfaces: DSI, DPI, DBI
- Read more... (pdf 673KB)
General Specifications
General Specifications of the TC358760XBG
| Supply voltages |
1.2 V (Core), 1.2 V & 1.8 V (MDDI® I/O),
1.8-3.3 V (I/O) |
| Package dimensions |
TC358760XBG: 3.5mm × 3.5mm (49 balls) |
| Status / Availability |
Mass production
|
DPI/DBI to DSI-Display Bridge / TC358763XBG
Features
- LCD-I/F: MIPI® DSI 3lane
- Multiple display bridges:
(DPI/DBI->DSI)
- Resolution: Up to qHD, HXGA (DPI-to-DSI mode)
- Read more... (pdf 668KB)
General Specifications
- Host I/F:DPI 24bit/DBI-B 16/18bit
- LCD I/F:DSI
General Specifications of the TC358763XBG
| Supply voltages |
1.2 V (Core), 1.2 V & 1.8 V (MIPI® I/O), 1.8-3.3 V (I/O) |
| Package dimensions |
TC358763XBG: 4.5mm × 4.5mm (72 balls) |
| Status / Availability |
Mass production
|
MIPI® Display Bridge / TC358762XBG
Features
- Host interface: MIPI® DSI
- Parallel display outputs: MIPI® DBI Type B, MIPI® DPI
- SPI, MIPI® DBI Type C and GPIOs for traditional peripheral interfaces, and I2C interface for internal register access
- qHD @70 fps (MIPI® DPI), FWVGA @60 fps (MIPI® DBI Type B)
- The source of the internal system clock is selectable from the DSI Clock or a clock derived by multiplying an external clock with on-chip PLL..
- Read more... (pdf 672KB)
General Specifications
General Specifications of the TC358762XBG
| Supply voltages |
1.2 V (Core), 1.2 V (MIPI® I/O), 1.8-3.3 V (I/O) |
| Package dimensions |
5.0mm × 5.0mm (64 balls) |
| Status / Availability |
Mass production
|
MIPI® DSI to LVDS Bridge / TC358764XBG, TC358765XBG
Features
- Host interface: MIPI® DSI (DSI RX 4 lane)
- Single Link(TC358764XBG), Dual Link (TC358765XBG)
- I2C (master) and GPIO interfaces for peripheral device control and I2C (slave) interface for on-chip register programming
- TC358764XBG : Up to WXGA resolution (1366 × 768, 24 bpp)
TC358765XBG : Up to WUXGA resolution (1920 × 1200, 18 bpp)
- Read more... (pdf 825KB)
General Specifications
General Specifications of the TC358764XBG, TC358765XBG
| Supply voltages |
1.2 V (Core), 1.2 V (MIPI® I/O),
3.3 V (LVDS I/O), 1.8-3.3 V (I/O) |
| Package dimensions |
TC358764XBG : 5.0mm × 5.0mm 0.65mm Ball pitch (49 balls)
TC358765XBG : 6.0mm × 6.0mm 0.65mm Ball pitch (64 balls) |
| Status / Availability |
Mass production |
MIPI® DSI to LVDS Bridge / TC358774XBG, TC358775XBG
Features
The TC358774/75XBG Functional Specification defines operation of the DSI2LVDS low power chip (or more abbreviated, 775XBG chip). 775XBG is the follow-up chip of TC358764/65XBG, which:
- Is pin compatible to TC358764/65XBG
- Exhibits LVDS Tx block operates at 1.8V @135 MHz to reduce operation power
- Updates 4-lane DSI Rx, max bit rate @ 1 Gbps/lane to support 1920 x 1200 x 24 @60fps
- Adds STBY pin with to enable turning on VDDIO power first before other power supplies.
General Specifications
General Specifications of the TC358764XBG, TC358765XBG
| Supply voltages |
1.2 V (Core), 1.2 V (MIPI® I/O),
1.8 V (LVDS I/O), 1.8-3.3 V (I/O) |
| Package dimensions |
TC358774XBG : 5.0mm × 5.0mm 0.65mm Ball pitch (49 balls)
TC358775XBG : 6.0mm × 6.0mm 0.65mm Ball pitch (64 balls) |
| Status / Availability |
Engineering samples available
|
MIPI® DSI to DisplayPort® TC358766XBG
Highlights
- DSI to DisplayPort® Bridge, D2DP, is used to convert a DSI or DPI video stream into a DisplayPort® interface one
- The target applications are devices with large Display Panels, such as MID, Tablet or PC
- The inputs are driven by a DSI Host with 4-Data Lanes @1 Gbps/lane or DPI Host with pixel clock @154 MHz (max)
- Up to WUXGA (1920x1200) @24-bit, 60fps with reduced blanking ? 3.7 Gbps
- Embedded I2S-type audio data into DP’s secondary packets
- Two DP data lanes are provided
- Can be used either as one link to drive a high resolution panel or as two links to drive two independent panels
- HDCP is used for content protection
- Debug/Test Port: I2C Slave
Features
- DSI-RX
- Support burst and non-burst mode Video Data
- Video data packets are limited to one packet/row per Hsync period
- Four Data Lanes with bi-directional support at Data Lane 0
- Maximum speed @ 1 Gbps/lane
- Video input data formats: RGB-565, RGB-666 and RGB-888
- Maximum video input frame size
- WUXGA (1920 x 1200) 24-bit @60 fps
- Does not support Interlaced video and deep color pixels
- DPI – parallel RGB input port
- MIPI DPI v2.00 Compliant
- Up to 16 / 18 / 24 bit parallel data interface
- Maximum Clock speed at 154 MHz
- Video input data formats supported:
- RGB-565, RGB-666 and RGB-888
- Read more... (pdf 821KB)
General Specifications
General Specifications of the TC358766XBG
| Supply voltages |
1.2V (Core), 1.2V & 1.8V (MIPI® I/O), 1.8V - 3.3V (I/O)
|
| Package dimensions |
TC358766XBG: 8mm x 8mm (100 pins), 0.65mm pitch, 1.2mm height
|
| Status / Availability |
Engineering samples available
|
MIPI® DSI to Display Port® Bridge - TC358770XBG
TC358770XBG receives two video streams coming via its dual MIPI® receiver and converts it into a Display Port® video stream.
Highlights
- Solutions are based on the latest versions of industry standard MIPI® DSI 1.01 and VESA DisplayPort® 1.1a
- Support for high-resolution DisplayPort® panels that require more than 4 Gbps data bandwidth
- Audio data is supported via I2S for an external DisplayPort® panel
- Applicable to portable products such as tablets and netbooks with high-resolution DisplayPort® panels
Features
- DSI RX Ports
- MIPI® DSI compliant version 1.01
- Supports two independent DSI RX ports
- Supports 1 to 4-data lane configurations per port
- Supports up to 1 Gbps per data lane
- Bidirectional support on Data Lane 0
- Receives and concatenates video packets from each DSI link and outputs them as one row of DisplayPort® video packet
- Video input data formats: RGB565, RGB666 and RGB888
- DisplayPort® TX Port
- VESA DisplayPort® 1.1a compliant
- Supports a four-lane main link for high bandwidth applications
- Supports data rates at 1.62 Gbps or 2.7 Gbps per lane of DisplayPort® link with voltage swings at 0.4, 0.6, 0.8 or 1.2V
- AUX channel supported at 1 Mbps
- Supports Audio related secondary data packets
- HPD (Hot Plug Detect) support through GPIO based interrupts
- SSCG with ~30 KHz modulation to reduce EMI
- Built in PRBS7 and color bar generators to test DisplayPort® link
- Supports HDCP encryption
- Support for audio related secondary data packets
- Audio Interface
- Either I2S or TDM Audio interface are available (pins are multiplexed)
- I2S Audio Interface
- Supports single stereo channel
- Supports 16, 18, 20 or 24-bit data
- Supports sampling frequencies of 32, 44.1, 48, 88.2, 96, 176.4 and 192 KHz
- TDM Audio Interface
- Supports single data link
- Supports 2, 4, 6 or 8 channels
- Supports 16, 18, 20 or 24-bit PCM audio data word
- Read more... (pdf 814KB)
General Specifications
General Specifications of the TC358770XBG
| Supply voltages |
1.2V (Core), 1.2V (MIPI® I/O),
1.8V (Display Port I/O) 1.8V (I/O) |
| Package dimensions |
5.0mmm x 5.0mmm 0.4mm Ball pitch (100 pins) |
| Status / Availability |
Engineering samples
|
Parallel RGB to MIPI® DSI Bridge - TC358768XBG
Features
- DSI-TX Interface
- MIPI® DSI compliant
- Support DSI Video Mode data transfer
- DCS Command for panel register access
(Version 1.02.00 – June 28, 2010)
- Supports up to 1 Gbps per data lane
- Supports 1, 2, 3 or 4 data lanes
- Supports video data formats
RGB888/666/565
- RGB Interface
- Supports data formats
- 24-bit data bus: RGB888/666/565 data formats
- Up to 166 MHz input clock
- Supports VSYNC/HSYNC polarity option
(default LOW)
- Supports DE polarity option (default HIGH)
- I2C/SPI Slave Interface
(Option to select either I2C or SPI interface)
- I2C Interface (when CS = L)
- Support for normal mode (100 KHz), fast mode (400 KHz) and special mode
(1 MHz)
- Can be used to configure all TC358768 internal registers
- SPI interface (when CS = H)
- SPI interface support for up to 25 MHz operation
- Can be used to configure all TC358768 internal registers
- GPIO signals
- 2 GPIO signals
Two GPIO signals can be configured as SPI signals (SPI_SS and SPI_MISO) or one GPIO signal can be configured as Interrupt output signal (INT)
- Power supply inputs
- Core and MIPI D-PHY: 1.2V
- I/O: 1.8V – 3.3V
- Package
- P-VFBGA 72-pin, 4.5 mm x 4.5 mm,
- 0.4 mm ball pitch, 1.0 mm height
General Specifications
General Specifications of the TC358768XBG
| Supply voltages |
1.2 V (Core and MIPI® D-PHY), 1.8-3.3 V (I/O) |
| Package dimensions |
4.5mm × 4.5mm (72 pins) |
| Status / Availability |
Mass production
|
Further Information
MPD (Mobile Peripheral Devices)
MIPI® word marks and logos are service marks owned by MIPI Alliance, Inc.
MDDI® is a trademark of the Video Electronics Standard Association (VESA)
DisplayPort® is a trademark of Video Electronics Standard Association (VESA)
Display Bridge/Hub