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Visconti™ Automotive Image Recognition Processor Series for Advanced Driver Assistance Systems (ADAS)

Visconti™ Series is an image recognition processor LSI for using camera-based vision systems.  Visconti™ Series detects and recognizes target objects such as pedestrians, faces, hands, vehicles and their motion/action by image processing image data from camera inputs frame by frame (including some previous frames in case of detection of motion/action), and then outputs recognition results by displaying results with marks on a camera image data to an LCD panel, alerting with voice message or beep, or reporting results to other units via communication I/F.

Visconti™ Series target products are systems using image recognition technology.  There are advanced driver assistance systems (ADAS) which are used to detect pedestrians, vehicles, traffic signs, etc. in the automotive market.  Surveillance cameras and security equipment which use pedestrian detection or identification with face recognition in the industrial market, and game machines which use hand gesture or motion capture in the consumer market.

Application examples of advanced driver assistance systems (ADAS) and pedestrian detection are shown below.  Visconti™ Series can realize various advanced driver assistance applications such as lane departure warning (LDW), forward/backward collision warning (FCW/BCW), forward/backward pedestrian detection (NV/BOP), traffic sign recognition (TSR) and so on by recognizing in real time traffic lines, vehicles, pedestrians, traffic signs etc. arround a vehicle using image data from 1 to 4 sets of cameras.

This figure provides an overview of the Visconti™ Automotive Image Recognition Processor Series.

Visconti™ Roadmap

This figure shows the roadmap of Visconti™ Automotive Image Recognition Processor Series.

Product Introduction: Visconti™ Series

Visconti™ Basic System Organisation

This figure shows the block diagram of a Basic System Organization using the Visconti™ Image Recognition Processor Series

Visconti™ Features

  • Heterogenous multi-core achitecture suitable for embedded image recognition systems.
    Visconti™ Series has the following different type of engines which can run simultaneously.  Therefore Visconti™ Series enables various image recognition applications in real time under low power consumption.
    • i. Image Processing Accelerators
      Visconti™ Series has image processing accelerator(s) which use image processing many times in each step of the image recognition flow and can operate at very high speed under low power consumption. Visconti™ has an affine transform accelerator that corrects lens distortion for fish-eye or wide angle lems and converts view-point.  Visconti™2 Series has not only the affine transform accelerator but also filter accelerators that reduces noises, detects edges, converts color space and so on, a histogram accelerator that makes histogram and a matching accelerator that calculates parallax using stereo image data and detects motion.  TMPV7506XBG of Visconti™2 Series has also a HOG(Histogram of Oriented Gradients) accelerator suitable for human detection, it can detect human who stood still in real time.
    • ii. Media Processing Engine (MPE) which uses Multi-grain Parallelism Architecture
      MPE consists of Toshiba original low power 32-bit RISC core MeP(Media embedded Processor) and MeP coprocessor suitable for multimedia processing such as image processing.  The MPE is a media processing engine which uses VLIW(Very Long Instruction Word) technology executes at same time multiple instructions including SIMD(Single Instruction Stream-Multiple Data Stream) instructions that operates multiple data simultaneously by one instruction.  Multi-core of MPE ( Visconti™ has 3 sets of MPE.  Visconti™2 Series has 4 sets of MPE.) executes simultaneously multiple applications with helping the above image processing accelerators and provides software solutions for implementation of various image processing algrithms.
    • iii. Control CPU
      Visconti™2 Series has various on-chip peripherals such as PCI Express, serial interfaces (UART?SPI?I2C) and so on.  Therefore a 32-bit RISC core "MeP(Media embedded Processor)" is added into Visconti™2 Series as a control CPU, and releases the above MPEs with controlling these on-chip peripherals by this CPU.
  • Provides a Software Development Kit (SDK) which supports the development of applications using C language.
    SDK includes various image processing libraries using the above image processing accelerators, device drivers for on-chip peripherals and tools such as C compiler, simulator for key modules of Visconti™ Series, etc.
  • Video input interfaces which connect multiple cameras and Video output interface which can synthesize multiple layers.
    Visconti™ Series can connect with up to 3 sets of 8-bit grayscale cameras.  Thereby Visconti™ Series enables simultaneously lane change assistance (LCA) application using left/right side cameras and forward or backward collision warning (FCW or BCW) application monitoring with a forward or backward camera.  Visconti™2 Series can connect up to 4 sets (TMPV7506XBG)/2 sets (TMPV7504XBG) of 8- to 12-bit grayscale cameras or high resolution (up to 1.3Mpixel) color cameras.  Thereby Visconti™2 Series improves recognition rate and enables traffic signal or sign recognition (TSR) applications that need color detection.  The TMPV7506XBG of Visconti™2 Series is suitable for a bird-eye view parking assistance application with synthesis of 4 camera image data.

Visconti™ Block Diagram

This is the block diagram of the Visconti™2 (TMPV7506XBG)

Visconti™2 (TMPV7506XBG)

This is the block diagram of the Visconti™2 (TMPV7504XBG)

Visconti™2 (TMPV7504XBG)

This is the block diagram of the Visconti™ (T5BG3XBG)

Visconti™ (T5BG3XBG)

Visconti™ General Specifications

 

Group Visconti™ Visconti™2
Product Name T5BG3XBG TMPV7504XBG TMPV7506XBG
CPU - Toshiba original 32-bit RISC CPU “MeP (Media embedded Processor)”
Image Processing Processors Media Processing Engine Toshiba Original Media Processing Engine “MPE” 3 sets Toshiba Original Media Processing Engine “MPE” 4 sets
Image Processing Accelerators Affine Transform 1ch 1ch
Filter - 2ch
Histogram - 1ch
Histogram of Oriented Gradients(HOG) - - 1ch
Matching - 1ch
On-chip Memory ROM - Masked ROM: 64KBytes
RAM - SRAM: 2080KBytes
On-chip Peripherals Video Input Interface Up to 3ch (Grayscale) Up to 2ch (Color/Grayscale) Up to 4ch (Color/Grayscale)
Video Output Interface 1ch (VGA size, RGB888) 1ch (WVGA size, RGB888)
Main Memory Controllers SDRAM Controller DDR2 SDRAM Controller
NOR Flash/SRAM Controller
External MCU Interface 1ch (8-bit bidirectional parallel I/O)
PCI Express - - 1 lane
CAN Controller - 3ch
I2C Interface - 4ch
UART Interface 1ch 5ch
SPI Interface - 4ch
PCM Interface - 2ch
Timer/Counter 4ch 11ch
Operating Frequency 150MHz 266MHz max.
Package BGA 456pins, 27mm×27mm BGA 516pins, 27mm×27mm

 

   
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