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Automotive Display Controllers

Toshiba's automotive display controllers are designed to provide the capability to display instrument clusters, heads up displays, navigation systems and other in-vehicle applications. The controllers integrate a CPU, a graphics accelerator and a variety of interfaces on one single chip. All of which have the unified memory architecture (UMA).

Display controllers available for low-end to high-end applications
64-bit CPU core
24-bit color depth plus 8-bit alpha blending
Powerful 2D/3D graphics accelerator
Controllers with an embedded DRAM eliminate the need for external graphics memory.
Distortion correction for fisheye-camera and heads up display
Camera/video input with scaler

This figure provides an overview of the Toshiba's automotive display controllers.

System Organization Example

This is the block diagram of the Toshiba's automotive display controllers.

System Features

Bus Architecture

This figure shows the on-chip bus structure of the Toshiba's automotive display controllers.

Provides high-performance solutions thanks to the graphics accelerator, independent graphics bus and embedded DRAM.

Graphics Engine Overview

This figure depicts the features of Toshiba's 2D graphics engine.

This figure depicts the features of Toshiba's 3D graphics engine.

Lineup

Feature	TX4966XBG-280	TX4964FG-120	TX4961XBG-240	TMPA970C20XBG
CPU core	64-bit RISC TX49/L4	64-bit RISC TX49/L4	64-bit RISC TX49/H3	Dual ARM CortexTM-A9
Operating frequency	280 MHz	120 MHz	240 MHz	266 MHz
Graphics accelerator	2D/3D (Hardware)	2D (Hardware)	2D (Hardware)	2D/3D (Hardware)
3D graphics	Open-GL ES 1.1	N/A	N/A	Open-GL ES 2.0
Camera/video inputs	2 ch	1 ch	1 ch	2 ch
Display outputs	2 ch	1 ch	1 ch	2 ch
A/D converters	N/A	N/A	Available	N/A
CAN controllers	4 ch	2 ch	3 ch	3 ch
MediaLB	Available	N/A	Available	Available
External memory	SDRAM	N/A	DDR SDRAM (512 MB max)	DDR2 SDRAM
On-chip memory	SDRAM 8 MB	SDRAM 4 MB	N/A	2 MB
Package	PBGA456	LQFP176	PBGA456	PBGA516
Operating temperature range	-40° to 85°	-40° to 85°	-40° to 85°	-40°C to 85°C

Product Introduction

Automotive Graphics Controller: TX4964FG-120

2D graphics accelerator
On-chip eDRAM
Reduced board assembly cost due to the QFP package

Features

CPU: 64-bit TX49/L4 core; 120 MHz
- No floating-point unit
4-Mbyte eDRAM
Graphics display controller with per-pixel alpha-blending
- 32-bit RGB alpha plane ×2
  8-bit CLUT plane ×2
  4-bit CLUT plane ×1
2D graphics accelerator
- Blit engine with alpha blending
  Rotation engine
  Transformation engine
Camera/video frame grabber
- RGB/YCbCr input interface
Peripheral modules
Communication modules:
- 2-channel full-CAN controller (TXCAN; two sets of 16 mailboxes)
- SPI (SEI) master/slave module with FIFOs
- SIO/UART with FIFOs
- 1-channel I²C module
- 2-channel I²S module
System control:
- 24-bit RTOS system timer
- Watchdog timer
- 3-channel 16-bit PWM timer
- 3-channel 16-bit timer
Package: LQFP-176-2424-0.5

This is the block diagram of the TX4964FG-120 Automotive Graphics Controller.

Automotive Graphics Controller: TX4966XBG-280

2D/3D graphics accelerator
On-chip eDRAM
Dual video inputs and outputs