Toshiba's CD/MP3 processors designed for car audio applications support multiple storage media, decoding of multiple audio formats and MP3 encoding to accommodate a wide variety of applications. To meet the car audio needs, the CD/MP3 processors use a low-leakage SRAM to reduce standby current. Additionally, there are CD/MP3 processors that integrate a DRAM in a package as a shock-proof memory. Support for various storage media links car audio, home audio and portable audio together and brings high sound quality and ease-of-use into cars.

Features

• Fabricated with the CMOS3E (0.13 µm) process ideal for audio SoC chips. Many IP cores are shared in common across ICs to improve design productivity.
• Enjoys significant market shares in Japan, Europe, North America and Asia, with a proven track record of volume production. Integrates a high-performance CD servo and a high-functionality audio DSP on the same chip to meet market needs.
• Decoders for MP3, WMA, AAC and ATRAC, industry's largest number of audio formats
  Supports leading-edge security solutions: iPod, MS-DRM and AAD Multi-DRM.
  Supports multiple storage media for easy compatibility and connectivity: CD-DA, CDMP3, SD and USB.
• Some chips integrate a shock-proof memory in a system-in-package (SiP).
• Uses a low-leakage SRAM as a buffer memory for compressed audio decoding, which also reduces current leakage in standby mode.

TC94A70FG: CD Servo + DSP

• CD section
• CD servo with RF head amplifier; 1x/2x/4x CLV/CAV
• DSP section
• 24-bit DSP core
• ISO 9660 disc authoring
• 1-Mbit SRAM (for data buffering and file management)
• Multi-codec (MP3, WMA, AAC, ATRAC)
• Audio outputs
• DACout, Aout (incl, I2S), Dout
• Power supplies
• 3.3 V (I/O, CD analog section, DAC)
• 1.5 V (CD, DSP core, memory)
• Clock
• 16.9344 MHz (single clock for the entire chip)

 

TC94A83FAG: CD Servo + DSP + MCU

• CD section
• CD servo with RF head amplifier; 1x/2x CLV
• DSP section
• 24-bit DSP core
• ISO 9660 disc authoring
• 1-Mbit SRAM (for data buffering and file management)
• Multi-decoder (MP3, WMA)
• MCU section
• 900/H1 core (instruction set fully compatible with 900/L1)
• 128-Kbyte ROM, 8-Kbyte RAM, SIO/UART, I2C
• Audio outputs
• DACout, Aout (incl. I2S), Dout
• Power supply
• 3.3 V (on-chip 3.3-to-1.5-V voltage regulator)
• Clock
• 16.9344 MHz (single clock for the entire chip)