Advanced Toshiba RF-CMOS technology offers lower unit cost and higher reliability compared to a traditional system-in-package (SiP) approach and combines this with the lower development risk and higher productivity of an innovative ‘hybrid’ customer owned-tooling (COT) business model.
The wish to be independent from cable-bound communication generates an unprecedented demand for high-speed, high-bandwidth portable communications products, which leads to a burgeoning market for integrated RF solutions. From nearline applications such as Bluetooth®, near field communication (NFC) and RFID for distances less than three metres, to 802.11a/b/g/n and local area network products spanning up to 100 metres wide area networking solutions such as WIMAX, and digital broadcast receivers, all aspects of the wireless communications market are experiencing growth. This rapid growth, in turn, is increasing demand for the cost, power and density benefits of integrated CMOS, analogue and RF devices.
Customer Benefits
Low Risk
- RF-CMOS experience since 1996
- Toshiba RF-CMOS technology available since 0.25?m and continuously developed for newer technologies
- 40nm RF-CMOS is the 6th RF-CMOS generation
- Very accurate models - excellent match between silicon and simulation
- In-house RF-CMOS experience from Toshiba’s own product development (Digital TV, WLAN, Bluetooth, mobile phone networks)
- Based on mature CMOS process - same physical transistors as pure CMOS but enhanced RF-CMOS models with additional terminals
- Process Design Kits (PDK) are mature and improved by feedback from internal chip developments
- Customers use the technology and PDKs that Toshiba uses for its own product development in the USA, Europe and Japan
- Access to Toshiba’s silicon-proven mixed-signal IP portfolio (including USB Phy, HDMI, SATA, PCIe, PLL, ADC, DAC, DDR1 and DDR2)
- Hybrid COT business model allows customers to use Toshiba’s silicon integration competence for digital logic and chip-level integration
High Performance
- Toshiba has experience with very high frequencies from both technology research and the development of products such as 60GHz mm-wave designs
- Ultra-thick Metal (UTM) process option for high-Q inductors
High Flexibility
- Hybrid COT business model allows flexible design-in and product-out
- PDK supports generators for scalable pcells and SPICE models
- Full access to Toshiba’s ASIC library (I/O pads, SRAM, ROM, ESD and latch-up structures)
- RF-CMOS technology can be combined with pure CMOS technology options including deep N-well, MIM cap, multi transistor Vth (low leakage, low power, high speed, very high speed, mid-range poly resistors)
Technology Overview and Selection Guide
|
| TECHNOLOGY NODE |
130nm |
90nm |
65nm |
40nm |
| MOSFET |
Vdd [V] |
1.5/1.2 |
1.2/1.0 |
1.2/1.0 |
1.1/1.0/0.9 |
| Ft [GHz] |
90 |
140 |
180 |
~250 |
Digital
Library |
Random
Logic Density
[kgates/sqmm] |
206 |
403 |
800 |
2100 |
6-tr SRAM
Cell Density
[squm/bit] |
2.5 |
1.25 |
0.495 |
0.24 |
Because the RF and mixed-signal components do not shrink much with geometry, smaller geometries do not bring significant advantages. This makes 130nm the most economic technology for standalone radio chips and other devices that combine RF and wired high-speed interface functions with a small amount of digital logic.
For special applications where the electrical performance of 130nm is not sufficient but there is not enough digital logic to justify a 65nm technology, 90nm is used.
The mainstream technology for RF-CMOS integration with large numbers of logic gates (e.g. digital baseband) including integrated memories and standard mixed-signal connectivity interfaces is 65nm. And, as production cost is nearly identical to that of 90nm technology, 65nm also delivers significant commercial advantage.
In cases where the design comprises a very large amount of digital logic, 40nm can be the right technology to reduce cost per chip compared to 65nm. Toshiba’s mixed signal and RF design kit for its 40nm process is mature and available for customer designs.
|
Toshiba’s RF-CMOS technology combines mature baseline CMOS processes with a fully-featured RF PDK. The RF module enables on-chip integration of passive elements such as MIM capacitors, junction and MOSFET varactors (deep N-well, single-end and differential), inductors (half turn, differential or symmetrical), mid-range poly resistors with zero temperature coefficients, and junction capacitors, as well as parasitic devices such as NPN transistors. Although Toshiba offers RF-CMOS technology from 250nm onwards, the mainstream technologies are 130nm and beyond since larger geometries cannot typically achieve the electrical performance required by current and future applications.
|
Supported EDA Environment
 |
Industry standard tools from leading vendors such as Cadence®, Mentor Graphics® and Agilent Technologies are supported by Toshiba's RF-CMOS PDKs. Support for other tools is available on request. |
Hybrid COT Model
As RF-CMOS functions have to be developed using basic transistors and passive components, the development model for RF-CMOS SoCs is the traditional COT model. In a COT flow, the developer contracts with a foundry and other third parties such as design houses, IP providers, packaging companies and qualification houses to design, fabricate, package and test it's custom-designed SoC.
Toshiba introduced a new flexible business and support model called "Hybrid ASIC / COT Model". Further details will follow soon, for the moment please see this first announcement at GSA event (May 2009 in Munich).
Shuttle Runs
To help validate a design prior to making the significant investment in production tooling, Toshiba offers frequent “shuttle runs” in which design blocks can be prototyped on a multi-project wafer. Once the prototype is approved, a dedicated mask set is created. Please contact the ASIC & Foundry team for further information on shuttle starts.
ASIC & Foundry RFCMOS Flyer (pdf 642KB)
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