Toshiba offers a variety of optimised PLL (phase locked loop), DLL (delay locked loop), SSCG (spread spectrum clock generator) and Oscillator IP blocks for different applications and voltage ranges. These include circuits for clock generation up to 2GHz, higher rates for embedded SerDes capabilities and optimisations for parameters such as low jitter, low duty cycle distortion, low power and low area.
- Local support by European Mixed Signal IP Department in Düsseldorf, Germany
- Team of highly skilled engineers, most with more than ten years of analogue design expertise
- Broad high end PLL portfolio originated from local HS-IO development over one decade
- Focus on Leading Edge Technology 40nm/65nm/90nm and availability down to 0.50µm
- Single voltage and single supply, no necessity for external components keeps board layout at minimum cost
- Low static phase error for precise clock alignment (de-skew) and clock multiplying
- Compliance to EMI market requirements resulting in reliable SSCG design
Toshiba PLLs are Leading Class in :
- Power Saving (<3mW)
- Low Jitter Performance (<4ps rms)
- Silicon Area (<0.2µm²)
The Mixed Signal IP Team in Düsseldorf is looking forward to support your request for customization to design an IC matching perfectly your application requirements.
Send your request for information to the ASIC & Foundry team
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