RTL to Gates & Handoff

The quality of RTL code and subsequent synthesis into Toshiba gates is key to smoothly implement the SoC. Toshiba offers a broad range of services and methodology support to facilitate the design hand-off. Apart from RTL coding style, netlist design rules and connectivity checks, we have newly introduced a comprehensive check of chip level timing and design constraints (SDC) deploying Atrenta SpyGlass. Constraints driving the physical implementation are verified for consistency and correctness. This helps to reduce the risk of unnecessary iterations due to wrong or incomplete deliverables to Toshiba.

Design Planning & Prototyping

During Design Planning and Prototyping the feasibility in terms of die size estimation, block partitioning, routing congestion and timing is verified. "Lean" algorithms are used to generate a physical prototype with fastest TAT while maintaining sufficient accuracy to allow a quick exploration of alternatives in the early design stages. Thus, a Go/No-Go decision for the final physical implementation can be made with best confidence. For highly complex or timing critical multi-million gate designs an optimum partition into hierarchical blocks and the top level is performed.

Physical Synthesis

In deep submicron technologies timing is dominated by wire delay realities. Physical Synthesis combines logic optimization with cell placement. Based on the actual placement interconnect delay can be estimated with much higher accuracy compared to simple statistical models. Thus, logic transformations, cell sizing and other optimizations are adjusted to actual physical needs and better timing and power results can be achieved.

Place & Route

Today, traditional Place and Route tasks have to be supplemented by signal integrity verification, yield enhancement techniques and low power solutions. Toshiba has a unique EDA platform to improve timing, resolve signal integrity problems, increase yield and perform various verification and optimization tasks. E.g. an advanced clock management methodology not only realizes skew-free clocks, but also cuts clock insertion delay, fixes electromigration violations and incorporates clock gating for power reduction.

Signal Integrity

Signal Integrity (SI) problems such as crosstalk and voltage drop are more and more emerging as first-order design issue that can cause functional failures in today's nanometer processes.

Voltage Drop Analysis and Prevention

As a design goes through the physical layout flow, it becomes more difficult to correct voltage drop errors. It is important to implement voltage drop prevention as early as possible in the design cycle. At Toshiba, we estimate voltage drop value at early design stages and implement various novel techniques to prevent them, such as optimizing power grid routing and comprehensively reducing chip's power dissipation. Even if the voltage does drop, we consider the impact as a margin of the timing analysis. Today both, static and dynamic drop analysis methods are applied.

Crosstalk Analysis and Prevention

Crosstalk is a pressing SI-related issue which causes device function failures and unpredictable delay side effects. Toshiba has effective crosstalk prevention, analysis and removal features integrated into the design flow at various stages.

DFM Solutions

The patterning resolution of lithography has not been able to keep pace with rapidly shrinking device geometries. Toshiba addresses such problems by using design-for-manufacture (DFM) from early in the design cycle. Yield and lithography centric enhancements are implemented throughout the entire flow. E.g. double cut vias can now be applied to improve the manufacturing yield of random logic regions during routing. Traditionally, only single cut vias were used.

Sign-Off Environment

To make it easier to take full advantage of Toshiba's deep-submicron silicon capabilities, we've gone to extraordinary lengths to make the Toshiba EDA environment a flexible, adaptable environment. Deep- and ultra-deep-submicron ASICs are supported by Toshiba's open EDA strategy based on sign-off on EDA tools from leading EDA vendors; Toshiba offers signoff-accuracy delay models and functionally-rich design kits.

Delay Calculation

In today's deep-submicron ASICs, delays caused by interconnect are becoming increasingly dominant over gate delays. To accurately calculate deep-submicron delays, new techniques must be used. At the 0.25-micron generation, coupling capacitances only between adjacent wires were extracted. Starting with the 0.18-micron generation, a 3D extraction technique is used. Furthermore, at the 90-nm generation, process variations are considered in extracting the 3D capacitance.

Evolving Wire Delay Models

In deep-submicron designs, long global interconnect lines become much more highly resistive as line dimensions are decreased. With shrinking process geometries, resistance shielding effects and waveform degradations have come to influence circuit delay. Toshiba's delay calculator models these effects in the circuit for accurate delay calculation.

Logic Simulation Sign-Off

The Toshiba Verilog and mixed VHDL/Verilog Sign-Off System can be used in combination with Cadence's Verilog-XL and NC-Verilog, Mentor Graphics' ModelSim and Synopsys' VCS. The simulation Sign-Off system comprises a complete sign-off framework and database providing proven functionality such as

  - design statistics
  - netlist check (e.g. electrical, connectivity, tester rules)
  - test pattern extraction and verification

for performing all the complex tasks needed to verify your logic design for Toshiba's ASIC & SoC solutions. It is simple to operate, yet sophisticated enough to handle the most complex designs today.

STA Sign-Off

Toshiba supports Synopsys' PrimeTime as an ASIC STA tool. Depending on process generations, on-chip variation analysis is performed, taking various effects of potential voltage drop and others into account. On-chip variation analysis is one of the static timing analysis techniques for considering delay variations.

Design-for-Testability (DFT)

Design Environments and Methodology to Generate High-Quality Test Patterns

To minimize the probability that defective chips are shipped, high-quality manufacturing test patterns are required. Toshiba supports popular design-for-testability (DFT) techniques such as internal-scan to help you facilitate test pattern development. You can choose how much of the DFT task you want to do yourself. If you have your own DFT tool, you can perform the entire DFT task at your site. Alternatively, you can entrust the DFT task to Toshiba, provided you create your design in compliance with test design rules.

Supported DFT Techniques

JTAG Boundary-Scan Design

JTAG boundary-scan is the most widely used board-level test vehicle defined by IEEE Std. 1149.1. Toshiba's ASIC cell offerings include a complete set of boundary-scan register (BSR) cells and several JTAG controllers.

Internal-Scan Design

Internal-scan transforms a design in a manner to enable automatic test pattern generation for combinational circuits. There are two categories of scan flip-flops from which you can select to implement internal-scan: area-oriented flip-flops and speed-oriented flip-flops.

Memory BIST Design

Toshiba offers a design environment to automatically insert BIST logic for on-chip SRAMs and mask ROMs. Features:

    1) Supports concurrent testing of multiple RAMs.
    2) Generates compact BIST logic at RTL.
    3) Automatically inserts the BIST logic to your design.
    4) Uses a robust test algorithm called March 13N with two data backgrounds.
    5) Allows you to freely specify the operating speed of BIST logic.

Toshiba inserts BIST logic for DRAMs for you. Features:

    1) Supports concurrent testing of multiple DRAM macros.
    2) Allows you to specify various test conditions.

Test Solutions

We provide you the design/test environment conforming to the international standard test description language STIL^*. We can use STIL output by Automatic Test Pattern Generation tool (ATPG), STIL generated by Simulator, and STIL supplied by IP vendor. So it is possible to use the test data efficiently. Therefore we can shorten the test data generation time, and we can reduce the test cost. Additionally we can shorten TAT from Design to Test and Failure Analysis by handling test data of each step with STIL.

Trademarks

*	STIL (Standard Test Interface Language) is a test data description language approved as IEEE std 1450-1999. STIL reads "style".
**	Mentor, Mentor Graphics and ModelSim are trademarks or registered trademarks of Mentor Graphics Corp.
***	Cadence, Verilog, Verilog-XL and NC-Verilog are trademarks or registered trademarks of Cadence Design Systems, Inc.
****	Synopsys, PrimeTime and VCS are trademarks or registered trademarks of Synopsys, Inc.
*****	Atrenta and SpyGlass are trademarks or registered trademarks of Atrenta

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