The CMOS (complementary metal oxide semiconductor) technology is the base for Toshiba’s custom LSI (large scale integration) products. Toshiba is continuously investing in fabrication capacity and advanced process development.

Toshiba CMOS Technology Roadmap for ASIC

• 40nm, 65nm, 90nm and 130nm are the mainstream technologies today
• The more mature technologies – from 0.18um to 0.6um are still in production
• RFCMOS PDK is available for 130nm, 90nm, 65nm and 40nm

Toshiba has already started process development for the technologies of geometries smaller than 40nm.  However, production of mature technologies, is still available for design starts.  Toshiba has no plans to discontinue production, (for example, 1.0um technology, introduced in 1986 is still in production.)

Note: The CMOS Technology roadmap is an interactive element. Please select the technology by moving your cursor over the image and you will get key feature / target applications listed in a text-box.

As a result of this long term strategy, a variety of technologies ranging from mature 0.4um down to advanced 65nm transistor channel length technologies are available for design start.  Customers can select the one that best fits their specific product requirements in terms of cost and performance, voltage/power constraints and cell/block availability.  Mature technologies offer high voltage options (18V/48V), later technologies offer several process options for low power, high speed, low leakage current and precise analogue functions.  All technologies support a wide range of different I/O (input/output) voltages.

More information about different technologies are available in our product flyer:

• 0.4µm (3V) CMOS ASIC Technology (TC200)
• 0.4µm (3V/5V) CMOS ASIC Technology (TC203)
• 0.3µm CMOS ASIC Technology (TC220-TC223)
• 0.18µm CMOS ASIC Technology (TC260)
• 0.13µm CMOS ASIC Technology (TC280)
• 90nm CMOS ASIC Technology (TC300)
• 65nm CMOS ASIC Technology (TC320)
• CMOS ASIC
• ASIC & Foundry RFCMOS Flyer (pdf 642KB)

If you require further information please contact the ASIC & Foundry team.

Structured ASIC

Toshiba offers a Structured ASIC (Application Specific Integrated Circuit) Technology, targeting one-to-one FPGA (Field-Programmable-Gate-Array) replacement.  Toshiba’s structured arrays support the rapid creation of high-performance, low-power system-on-chip (SoC) devices through the customisation of only a small number of metal mask layers.  Minimising the number of metal layers that need to be customised reduces the minimum sample delivery time and has a significant impact on non-recurring engineering (NRE) costs.
Further details can be found here

Toshiba CMOS Technology for Foundry

Toshiba's Iwate plant offers foundry service for technologies from 0.6um to 90nm 8" wafer.  Besides PDK and digital/mixed signal libraries and IP, also special process developments and modifications following customers specifications are possible (ie. Special substrate, special process module, special layer stacks and post processing steps such as protection films and microlenses).
Further details can be found here.

ASIC with Stacked dRAM Die for High Bandwidth Access

By stacking modified standard dRAM dies of 512Mbit to 2Gbit with microbumps on logic ASIC dies, customers can achieve memory access bandwidths up to 400Gbit/sec at less than 5W of total power.
Further details can be found here.

RFCMOS Technology

Toshiba’s RF-CMOS technology combines mature baseline CMOS processes with a fully-featured RF PDK.  The PDK's are available for 130nm, 90nm, 65nm and 40nm.  Further details can be found here.

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