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System-in-Package (SiP)

System-in-Package (SiP) provides a solution to system design challenges.  SiP helps surpass the limits of the conventional System-on-Chip (SoC) designs.  More information is included in the SiP - System in Package Flyer (pdf 725KB)

SiP Features / Benefits

  • User IP integration
  • Mixed analog / digital design
  • IP re-use = shorter time to market
  • Integration of large memories = lower design risk (ease of re-design)
  • Reduce process complexity = lower development cost
  • Reducing system board space
  • Reducing board mounted height

Stacked Chip SoC (SCS)

For applications requiring a higher bandwidth than is achievable with external memory or wire-bond based SiP, Toshiba offers Stacked Chip SoC (SCS) technology.  The SCS approach uses specific DRAM dies modified by Toshiba, which are attached onto the logic chips through microbumps (bump-attach).  These microbumps are all located in a single plane and with this set-up it is possible to implement up to several hundreds or even thousands of connections.  As a result, the entire bit width of the internal RAM organization (512bits to 2048/1024bits, separate for read and write) can be connected through this interface directly with the logic chip's internal interface  – without the conventional multiplexing into 16 or 32 external bits and without the necessity for any drivers, ESD protection structures and level shifters.  This approach makes it possible to implement high access bandwidths concurrently with low power dissipation.

Present configurations in terms of capacity/interface are 512Mbit/512bit, 1Gbit/1024bit and 2Gbit/2048bit.  At a single data rate interface speed of 160MHz, this results in maximum achievable bandwidths of 80Gbit/s, 160Gbit/s and 320Gbit/s , respectively.  The power dissipation of the interface and DRAM chip in such an SCS configuration is 80% lower than for a comparable solution based on external DDR2 components.

Today the achievable memory bandwidth of conventional 16/32/64bit DDR2/3 based systems is in the 10-40Gbit/s range.  The combined power consumption of the controller on the SoC, interface and DRAM component in such a configuration is several Watts.  Faced with emerging image processing and communications applications that require memory bandwidth in the 100-400Gbit/s range, a DDR2/3 (or even GDDR5) approach would need an interface running into hundreds of bits and consuming tens of Watts.  SCS technology provides an effective and power-efficient alternative.

 

Stacked Chip SoC

Package-on-Package (PoP) Solutions

Toshiba provides package-on-package stacking solutions.  This approach helps to combine off-the-shelf packages on top of a logic chip that constitutes a major part of your system.

PoP Technology

Benefits

  • PoP is very flexible solution, as different devices can be mounted to a very small system, resulting in different system setup and features.
  • High yield due to individual tested devices.
  • Due to short I/O distance, even low power I/O ports can achieve high bandwidth data transmission, so overall power consumption is small.

Multi-Chip-Package (MCP)

Toshiba’s SiP solution fully leverages its advanced die back grinding technology to allow up to 9 layer - 5 die stack.  The integration of large memories lower the design risk (ease of re-design), reduces process complexity (lower development cost), reducing system board space and mounted height.

Toshiba side-by-side laminate type SiP package focus on mixed analog / digital design and user IP integration (IP re-use), which enables shorter time to market.

Toshiba side-by-side laminate type SiP package.

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