System-in-Package (SiP) provides a solution to system design challenges.  SiP helps surpass the limits of the conventional System-on-Chip (SoC) designs.  More information is included in the SiP - System in Package Flyer (pdf 725KB)

SiP Features / Benefits

• User IP integration
• Mixed analog / digital design
• IP re-use = shorter time to market
• Integration of large memories = lower design risk (ease of re-design)
• Reduce process complexity = lower development cost
• Reducing system board space
• Reducing board mounted height

Multi-Chip-Package (MCP)

Toshiba’s SiP solution fully leverages its advanced die back grinding technology to allow up to 9 layer - 5 die stack.  The integration of large memories lower the design risk (ease of re-design), reduces process complexity (lower development cost), reducing system board space and mounted height.

Toshiba side-by-side laminate type SiP package focus on mixed analog / digital design and user IP integration (IP re-use), which enables shorter time to market.

Package-on-Package (PoP) Solutions

Toshiba provides package-on-package stacking solutions.  This approach helps to combine off-the-shelf packages on top of a logic chip that constitutes a major part of your system.

Benefits

• PoP is very flexible solution, as different devices can be mounted to a very small system, resulting in different system setup and features.
• High yield due to individual tested devices.
• Due to short I/O distance, even low power I/O ports can achieve high bandwidth data transmission, so overall power consumption is small.

Chip-on-Chip (CoC) Solutions

Chip on Chip structure SiP (System in Package) with die-to-die connection by micro bump.  Allows very high band width chip-to-chip data transfer by very high pin count die-to-die interconnect and lower power solution than separate components.

Benefits

• Low package height.
• Low power I/O ports can achieve high bandwidth data transmission due to short I/O distance, so overall power consumption is small.

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