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Universal Array

…for effective, high-performance platforms, re-usability, fast development TAT, and minimum design risk

Universal Array is a flexible system-on-chip (SoC) design platform that significantly reduces the development time for SoC devices.  By applying Universal Array , Toshiba has cut the turn-around-time for production of engineering samples for 130nm and 90nm process technology significantly.

  • Provides chip size and performance comparable to cell-based ICs.
  • Uses the same cell library as for Toshiba’s cell-based ICs.
  • Achieves low power consumption comparable with cell-based ICs.

All cell-based ICs have to undergo a rigorous verification and testing process prior to production, a process that is as essential as it is time-consuming.  Conventionally, once the design process reaches tape out, the point where EDA tools can be applied to production of engineering samples of ICs, the diffusion wafer (DW) that integrates the basic IC components is fabricated, and the wafer then undergoes personalization (personalized wafer, PW) to complete the manufacturing process.  Universal Array shortens this process time by allowing fabrication of the DW at the same time as the implementation and timing verification processes.
 

Turn around time of engineering samples with Universal Array

1.  Reduces the turnaround time of engineering samples

  • With UniversalArray, diffused wafer (DW) fabrication starts before detailed layout of the logic portion of a chip is completed. This helps to reduce turnaround time between personalized wafer (PW) tape-out and the availability of engineering samples.

2.  Reduces the turnaround time of design spin-offs

  • With UniversalArray, the logic gate portion of a chip can be modified through only routing layers; even extensive ECO is possible. This helps to reduce the time required for mask tooling and chip manufacture.

3.  Reduces cost for design spin-offs

  • UniversalArray reduces the number of masks required for design spin-offs, cutting the rework cost.

No Compromises in your System

Processor Subsystem Design combined with Universal Array and prototyped with “Toshiba unique fast and low cost prototyping solution” helps the customer to:

  • concentrate on his core competence - the application
  • get an application specific platform for derivatives and further modification
  • get highest performance with lowest unit price
  • reduce development risk
  • shorten turn-around-time (TAT) by parallel process execution for test, verification and design

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