To meet the ever-increasing demands for higher levels of system
integration, semiconductor packages have evolved from through-hole
to surface mount types, and from peripheral-leaded to area array
formats. Additionally, the growing and diversifying system
requirements have continued to drive the development of a variety of
new package styles and configurations.
- Small-form-factor and lightweight technology
- Low-profile technology
- High-pin-count technology
- High-speed technology
- Thermal dissipation technology
Package Line-up
Toshiba‘s package line-up covers the entire range of
packages, optimized for different applications and constraints:
- Very small QON and Thin-QON packages for mobile and
handheld applications
- Chip-size packages (PFBGA – plastic fine pitch ball grid array)
for ball-counts up to 400
- Quad Flat Packs and Plastic BGA for general purpose, up to
high-end Flip Chip BGA with several 1000s of balls.
Further details for Toshiba's package line-up:
- PBGA - Plastic Ball Grid Array
- PBGA[FC] - Flip-Chip BGA
- PFBGA - Plastic Fine-Pitch BGA
- QFP - Quad Flat Package
- QFN/QON - Quad Flat Package / Quad
Outline Non-Leaded
- WCSP - Wafer level Chip Scale
Package
More information is included in
System LSI
Package Flyer (pdf 738KB)
Package Performance Map
Electrical and Thermal Balance
Ultimately, FCBGA has the best
thermal and electrical performance, however it is also the most
expensive solution. PBGA is cost
effective, but has relatively less performance than
FCBGA. 4-layer PBGA can improve the
thermal/electrical performance. PFBGA
is smaller so it can be expected to have lower RLC. The thermal
performance is not as good as other packages.
Package Technology Trends
Small and thin packages with high function density are key for
competitiveness in mobile and handheld applications. Toshiba
supports these trends by offering thinner QON and Fine-pitch BGA and
smaller ball pitch down to 0.5mm (leading to smaller package
outline). Ultimately, stacked die‘s in these packages (SiP – System
in package technology) achieves the highest function density.
More information about System-In-Package (SiP).
Chip-Package-System (CPS) Co-design / Co-verification
Technology
Toshiba has developed a chip-package-system (CPS) co-design /
co-verification platform. Its concept is collaborative
development of the chip, package and PCB system board by creating an
accurate virtual package model before the designing of a package
substrate begins based on the final specification of the integrated
chip-package design. Chip-package-system co-design allows
optimal cost / performance trade-offs, reduces IC and system
development times and improves verification accuracy prior to actual
system hardware prototyping.
Further information about Chip-Package-System (CPS) co-design /
co-verification
RoHS Statement For ASIC
All new ASIC designs at Toshiba will be RoHS compliant and
leadfree solderable. For existing ASIC designs, please
contact your local Toshiba sales office for further assistance.
Further information
about Toshiba and WEEE, RoHS
Further information on phased out substances
Glossary
- Cavity - Active side of a die
- CoC - Chip-on-Chip
- FBGA - Fine-Pitch BGA
- FCBGA - see PBGA[FC]
- LQFP - Low Profile Quad Flatpack (1.4mm)
- PBGA - Plastic Ball Grid Array
- PBGA[FC] - Flip Chip Plastic Ball Grid Array
- PoP - Package-on-Package
- PQFP - Plastic Quad Flatpack
- P(T)FBGA - Plastic (Thin) Fine Pitch Ball Grid Array
- PTP - Paper-Thin-Package
- QFN - Quad Flat Non-leaded Package
- (T)QON - (Thin) Quad Outline Non-Leaded
- QFP - Quad Flat Package
- SiP - System-in-Package
- WCSP - Wafer level Chip Scale Package
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