Chip-Package-System (CPS) - Co-Design Flow of Chip and Package

The introduction of BGAs, with an array of solder balls underneath the package, has allowed package pin count and density to increase.

A similar migration, from perimeter pads to an area array format is necessary at the silicon to package interconnect level to achieve reasonable die sizes and meet silicon/package electrical performance requirements for high end designs now requiring 600 - 2400 pins.

Flip chip, placing an array of solder bumps underneath the die, offers the shortest interconnect path (i.e., low inductance) and highest I/O density available. (Note: Die is “flipped over” with active silicon side and solder bumps facing down).  Using build-up technology organic substrates designed with multiple power, ground and signal layers while providing an efficient heat transfer path directly from the back side of the die to a heat sink, the PBGA[FC] can handle the most serious high performance design challenges.

Features:

• Most enhanced solution with respect to. electrical and thermal performance
• Very flexible substrate design (impedance/noise control for HS I/F)
• Ball count: 625 – 2304 balls
• Body size: 27 x 27/31 x 31/35 x 35/40 x 40/45 x 45 mm², 1.00 mm pitch
• Cavity: cavity down
• Substrate: 6 or 8 layers
• Up to 10W power consumption
• Target Area: High-speed I/Os, telecom applications, high-end products

Benefits:

• Best electrical and thermal performance available
• Suitable for high end application
• Particularly suitable where high speed interfaces are required

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