Chip-Package-System (CPS) - Co-Design Flow of Chip and Package

PBGA packages are available with 256 to 1,000 pins to target high-pin-count applications.

PBGAs can be mounted using standard surface mount equipment. Compared to conventional packages such as QFPs, PBGAs offer reduced skew and lead coplanarity assembly problems, leading to lower surface mount defect rates.  PBGAs are suitable for many ASIC applications and are the most popular package in use today.

PBGA packages have a two- or four-layer substrate with power and ground rings. Power/ground pads on the die are wire-bonded to the power/ground rings on the package substrate.  This helps to reduce noise, making PBGAs well suited for high-speed designs.

Features:

• Improved thermal resistance with thermal balls added
• Ball count: 256 – 1000 balls
• Body size: 23 x 23 - 40 x 40 mm²
• Ball pitch: 1.00 mm/1.27 mm
• Cavity: cavity up
• Substrate: 2 or 4 layers
• Up to 4W power consumption

Benefits:

• Best ratio in cost, electrical and thermal performance
• Particularly suitable where high speed interfaces are required

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