Toshiba offers a large portfolio of basic mixed-signal cores. Our local mixed-signal engineering expert team supports:
- Q&A around applications and feasibility studies
- Implements and adapts / customize IP for specific applications
Special I/O Cells
In addition to standard I/O cells (including LVTTL, CMOS and cells offering different drive strengths, slew rates, voltage levels and pull-up resistor options), Toshiba also offers off-the-shelf and customised IP to address I/O requirements such as:
- Oscillator circuitry
- Non-standard I/O voltages
- 5V-tolerant operation
- ESD protection
To reduce the complexity of the power supply system for advanced SoC designs, and to save material cost in price-sensitive consumer applications, Toshiba offers base IP for integrated voltage regulation in the form of hard macros for LDO regulators.
As requirements, specifications and optimisation requirements for voltage regulation differ from project to project, Toshiba also offers an individual customisation service for this class of IP.
Toshiba offers a variety of optimised ADC (analog to digital converter) and DAC (digital to analog converter) for various applications, voice codec and audio DAC.
Further details on ADC / DAC
Toshiba offers a variety of optimised PLL (phase locked loop), DLL (delay locked loop), SSCG (spread spectrum clock generator) and Oscillator IP blocks for different applications and voltage ranges. These include circuits for clock generation up to 2GHz, higher rates for embedded SerDes capabilities and optimisations for parameters such as low jitter, low duty cycle distortion, low power and low area.
Further details on PLL/DLL/SSCG
Customer-Developed Mixed-Signal IP
For customers looking to develop their own mixed-signal solutions, Toshiba can provide a Process Design Kit (PDK) for the required technology node, as well as evaluation, verification and qualification support to ensure the IP meets the same strict quality and stability criteria as the company’s own IP.
This allows customers with core competencies in mixed-signal applications ranging from RF-CMOS to high-speed design to minimise risk and reduce TAT by developing their own mixed signal IP hard macros that are optimised for integration with Toshiba’s SoC technologies.
More about this Hybrid ASIC/COT approach will follow soon.
Send your request for information to the ASIC & Foundry team
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