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MIPS Based RISC Cores

MIPS (Microprocessor without Interlocked Pipeline Stages)

Toshiba offers a complete family of MIPS-based reduced instruction set computer (RISC) microprocessors and peripherals. The processor core for ASIC are implemented as hard-macro based on our MIPS instruction set architecture (ISA) licence. They are fully object-code compatible. A huge set of peripherals used in ASSP can be selected. The peripherals are linked with Toshiba specific G-Bus and Sys-AD interfaces.

TX System RISC Core Roadmap
TX19 Family
TX39 Family
TX49 Family
TX99 Family
Toshiba licence synthesizable MIPS cores (24KEc and 24KFc) for next-generation digital consumer application. Please contact the ASIC & Foundry Team for support of synthesizable MIPS cores in your ASIC project.

TX19 Family

The TX19 Family consists of extremely compact, high-performance 32-bit microcontrollers development by Toshiba based on the MIPS architecture. The TX19 Family adds support for MIPS16TM (object code compatible) Application-Specific Extensions (ASE), a highly efficient code compression mechanism, to the TX39 Family. The TX19A core, with an expanded instruction set and improved performance, is also available.

TX39 Family

The TX39 Family of 32-bit RISC microprocessors for embedded use was developed by Toshiba based on the R3000A architecture designed by MIPS Technologies, INC.. The hard-macro TX39 core includes built-in cache memory.

TX49 Family

The TX49 Family of RISC microprocessors for embedded use is an original Toshiba 64-bit processor family and is based on the R4000A architecture designed by MIPS Technologies, Inc. The TX49 Family is upward-compatible instruction set including MIPS I, MIPS II and MIPS III instruction set architecture (ISA). The hard-macro core is available with different built-in primary cache memory configurations. All cores with debug support (EJTAG) and partly with floating-point unit (FPU).

TX99 Family

The TX99 Family of RISC microprocessors is based on the MIPS64TM microarchitecture of MIPS Technologies, Inc. The TX99 Family have a 64-bit superscalar architecture developed jointly by MIPS and Toshiba. The hard-macro core is based on MIPS 25Kf high-end RISC core and is instruction set compatible with MIPS64TM with MIPS-3DTM Application-Specific Extensions (ASE).

dual issue superscalar 7-stage pipeline
Primary cache memory
Level 2 cache optional
Floating point co-processor (FPU)
SoC interfaces via switch matrix

More details about the TX19, TX39, TX49, and TX99 families could be found at the micro-controller (ASSP) home page on the Toshiba Semiconductors Japan web site.

ASIC & Foundry