Toshiba has been a Mobile Industry Processor Interface (MIPI®) Alliance member since 2004. Since then, the company has developed technologies and in-house expertise that provides customers with complete MIPI-compliant solutions encompassing both the physical layer and the various MIPI® protocols.
Toshiba has already demonstrated its ability to deliver MIPI®-compliant technologies in a number of customer designs as well as its own application specific standard products (ASSPs). Based on the company’s advanced 90nm, 65nm and 40nm CMOS ASIC technologies, Toshiba MIPI®-compliant ASSPs include devices for display sub-systems as well as camera applications. Toshiba provides both physical layer and protocols that support the rapid development of complete MIPI®-compliant transmit and receive solutions.
ASIC & Foundry MIPI Flyer (pdf 1339KB)
A scalable, bi-directional, low-power, high-speed physical layer upon which several MIPI® interface standards are based (see below). The same D-PHY can be used for hi-speed serial communications in high speed mode and with single-ended transmission lines in low power mode. This makes it ideal for implementing a variety of different applications, including next-generation camera designs and high-speed display communications.
CSI-2 (CAMERA SERIAL INTERFACE 2)
Based on D-PHY, CSI-2 provides the interface between a camera module and, for example, the system host. The low pin count of CSI-2 enables camera signals to be carried across the limited conductors in the flex circuits of flip phone hinges. A total data rate of the link as high as 4Gbps enables new camera features and support sensor resolutions beyond 10Mpixel.
DSI (DISPLAY SERIAL INTERFACE)
Building on the core advantages of the D-PHY technology, DSI is a higher layer protocol with error correction that provides solutions for display-related data communication. DSI supports both “smart” (buffered) and “video mode” (unbuffered) display panels. The MIPI® Alliance has specified a specific DCS (display command set) that sits above the DSI and defines a standard software interface for different suppliers.
UNIPROSM (UNIFIED PROTOCOL)
UniProSM is PHY-independent and provides a single, unified reliable protocol that can be used across several applications including cameras, displays and device communication interfaces. UniProSM offers high-speed communications, error correction for reliability, and low energy per transferred bit. Currently UniProSM provides point-to-point functionality, but future generations will support network capabilities. Fully compatible with the existing D-PHY, UniProSM will also support future, higher speed M-PHY implementations.
Toshiba will continue to develop solutions for future MIPI® protocols as they become available.
Toshiba also offers a variety of additional IP in support of MIPI® solutions, including optional PLL IP, lane control and interface logic.
This PHY is compliant with the MIPI-D-PHY specification and provides a re-usable physical layer solution with support for one to four data channels and a single clock channel. MIPI® camera interfaces (CSI-2), display interfaces (DSI) and Unified Protocol (UniProSM 1.0/1.1) are based on the MIPI-D-PHY.
In High Speed (HS) mode the MIPI-D-PHY can deliver from 80Mbps up to 1Gbps per lane (depending on implementation and technology) via an advanced source-synchronous, differential SLVS transceiver which is scalable to the number of lanes required by the application.
In Low Power (LP) mode the D-PHY offers single-ended transmission speeds up to 10Mbps. Depending on the application operational power is in the mW range and standby power is in the ?W range.
D-PHY meets the requirements of low-power, low emission, and high-noise immunity that mobile phone designs demand. Based on 1.2V supplies, it scales well across future semiconductor process technologies.
Contact the team for further information
MIPI® marks and logos are service marks owned by MIPI Alliance, Inc. and any use of such marks by Toshiba is under license. Other service marks and trade names are those of their respective owners.
||4 wires only unidirectional or half-duplex
||<30 cm PCB, flex,
|Data rate per lane
||>80 Mb/s - up to 1 Gb/s
|HS Clocking Method
||DDR Source-Sync CLK
|HS Line Coding
||None or 8b9b
|Receiver CDR Required
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