Commonly employed in flat panel display (FPD) designs, LVDS is a signalling method for providing high-speed transmission of binary data over copper lines.  The low-voltage differential swing is used to deliver higher transmission speeds and inherently higher bandwidths at lower power consumptions when compared to conventional single-ended transmission technologies. 

Flat Panel Display (FPD) LVDS Transmitter Dual Link

Offering seamless integration into Toshiba’s advanced TC320 65nm (CMOS5) 1.2V low-power process, this IP block can convert up to 60 bits of RGB picture signal data and up to 12 bits of control signal data into 10 or 12 low-voltage differential swing (LVDS) streams.

In Dual Link mode at a transmit clock frequency of 85MHz, 72 bits of RGB and control data can be transmitted at an effective rate of 595Mbps per LVDS channel.

Features and Benefits Dual LVDS transmitter link Input clock range: 25~85MHz Optional scalable channel setup (on customer request) Parallel to serial data conversion included Integrated high-speed clock generation (no requirement for external components) Bandwidth up to 7.15Gbps with dual link Power down mode (Individually selectable for each channel’s serializer+LVDS buffer) Frequency range selectable for optimum feedback divider / pre-divider / output divider ratio of high-speed clock generation block Output swing selectable: Normal range (250~450mV) and reduced range (150~300mV) Output tri-state switchable Integrated test mode, scan mode for logic, direct access and bypass functions Integrated test circuits for BIST (Built-In Self Test) 1.2V and 3.3V power supply Typ.TX power per channel: 30mW Power down mode: typ. TX power < 1mW Integrated clock generation / Common block power: 20mW Channel skew: Values of < 75ps can be achieved through appropriate package design Differential skew: Values of < 20ps can be achieved through appropriate package design

Flat Panel Display (FPD) LVDS Receiver Link

Offering seamless integration into Toshiba’s advanced TC320 65nm (CMOS5) 1.2V low-power process, this IP block receives synchronous data along with the corresponding pixel clock information via an LVDS interface.

Incoming data is sampled by an internally generated high-speed clock and differential serial data is converted into a 7-bit parallel CMOS output for each channel by each pixel clock cycle.

This IP supports single link transmission between the host and the LVDS link at clock speeds of up to 150MHz. For frequencies below 20MHz, the cell offers LVDS feed-through signals to the SoC core. An on-chip high-speed clock generation block is used to multiply the received clock signal and synchronise it with the incoming data.

Features and Benefits LVDS receiver link 20MHz to 150MHz dot clock up to SXGA+ (1.05Gbps per channel) Optional scalable channel setup (on customer request) Open input detection for LVDS cells Serial to parallel data conversion included Integrated high-speed clock generation block: no requirement for external components Multi purpose I/O (LVDS or dual individual standard CMOS 3.3V inputs) Optional: LVDS on-chip termination Frequency range selectable for optimum setup of DLL Power down mode: typ. RX power < 1mW Typ. RX power: < 210mW (5 data channels incl. clock and DLL@85MHz) Test mode, scan mode for logic, boundary scan and bypass functions integrated Data/clock functional feed through mode 1.2V and 3.3V power supply

Flat Panel Display Driver Flyer (pdf 335KB)

Back to top
Back to ASIC & Foundry Home