Embedded SRAM/ROM

For each ASIC Technology, Toshiba offers a variety of different embedded SRAM, Registerfile and ROM architectures.  Each architecture is optimized for the variety of specific applications, such as high density, high speed, low power, efficiency for small blocks, efficiency for large blocks, single port, dual and multiport access.  All can be compiled in a wide range of words and bits.  For larger blocks, the redundancy feature (repair of faulty bits by usage of laser fuse at die sort testing) is available to ensure highest possible production yield.

Toshiba Memory BIST

The main purpose of a memory build-in-self-test (BIST) is to reduce production cost by reducing test cost and increasing the production yield.  A memory BIST allows to drastically reduce the test cycle duration by e.g. parallel testing of multiple memories and simplifies the complexity of the test and probe setup due to an extremely small number of required external pins.  This results in a sharply decreased overall test cost.

Furthermore the Toshiba Memory BIST allows to build fail maps for fault diagnostic, which helps to tune the process in the right direction and hence increase the production yield.  Toshiba developed a tool chain that automatically generates the RTL code of the BIST controllers and memory collars.  These modules are automatically inserted into the customer design by the Toshiba tools and can be verified with logic simulation.

Toshiba Embedded Memory

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