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Embedded Memory

Embedded SRAM/ROM

For each ASIC Technology, Toshiba offers a variety of different embedded SRAM, Registerfile and ROM architectures.  Each architecture is optimized for the variety of specific applications, such as high density, high speed, low power, efficiency for small blocks, efficiency for large blocks, single port, dual and multiport access.  All can be compiled in a wide range of words and bits.  For larger blocks, the redundancy feature (repair of faulty bits by usage of laser fuse at die sort testing) is available to ensure highest possible production yield.

 

Toshiba Embedded Memory

  SRAM Register Files ROM
0.6µm
TC190
Asynchronous SRAM,
Synchronous SRAM,
1-Port SRAM,
Dual-Port SRAM
Dual-, Three- and Four-Port Register Files
in flexible configuration
Several types of ROM available
0.4µm
TC200/TC203
0.3µm
TC220/TC223
0.18µm
TC60
High-density 1- and 2-Port SRAM,
High-speed 1- and 2-Port SRAM, redundancy SRAM,
bit-write capability option
Dual-, Three-, Four- and Five-Port Register Files
in flexible configuration
Compilable ROM,
flexible configuration up to 1Mbit
0.13µm
TC280
High-density 1- and 2-Port SRAM,
High-speed 1- and 2-Port SRAM,
Optimized High-speed/ High-density SRAM,
Redundancy SRAM,
bit-write capability option
 
90nm
TC300
Dual- and Three-Port register files, special register files on request
65nm
TC320


 

Embedded DRAM

EDRAMToshiba is the leader in embedded DRAM technology and is currently shipping its fifth generation of product in high-volume production.

Toshiba EDRAM Features And Benefits:

  • High performance with fast data transfer rates due to wide on-chip memory buses
  • Much denser than SRAM
  • Low power
  • Low Soft Error Rates (SER)
  • Multiple cores per chip
  • System architecture optimization and reduction of discrete components
  • Easy and effective testing with a direct-access test and DRAM BIST
  • High yield through redundancy in DRAM macros
  • Various types of DRAM macros with configurable depth and width
  • Trench process - one transistor DRAM cell structure utilizes trench process.  The trench capacitor allows for a planar surface topology that enhances reliability without compromising logic performance
  • High bandwidth - freed from I/O restrictions, embedded DRAM cores provide high-memory bandwidth with asynchronous interface and a bus width
  • selectable from 64-, 128- and 256 bits.
  • Configurable Macros - DRAM macros are configurable in depth and width to suit particular application requirements

Further details could be found in the CMOS ASIC Flyer (pdf 1100KB).

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