No system with micro-controller works without memory!  Toshiba offers a wide line-up of various types of embedded memory.

• Random access vs. block access
• Read/write vs. read-only
• One-time-programmable vs. Multiple-write cycles

• Embedded SRAM/ROM
• Embedded DRAM
• eFUSE - Electrical Programmable Fuse
• Non-Volatile-Memory (NVM)

You did not found the right embedded memory solution in our line-up? Have you tough about System-in-Package (SiP)? If yes, take a look into our offerings and consider also chip-package-system (CPS) co-design / co-verification and a modified testing strategy.

System-in-Package (SiP)

With increasing demands for higher system integration and single-chip implementation, semiconductor packages are not mere die housings any longer; they have become more of a crucial part of a system design. Toshiba offers a broad range of package options to satisfy all application needs, including system-in-packages (SiPs) specifically designed for high-end mobile devices and many other high-pin-count, small-form-factor and low-profile packages.

If you are confronted with contradictory needs, large memory, special memories, system performance and size reduction.  System-in-packages (SiPs) provide an ideal solution in such situations.  You can mix a variety of components such as logic and memory functions in a single package in side-by-side
and stack-up configurations to save board space.  

Further information about System-in-Package (SiP) or send your request for information to the ASIC & Foundry team

Chip-Package-System (CPS) Co-design / Co-verification Technology

Toshiba has developed a chip-package-system (CPS) co-design / co-verification platform. Its concept is collaborative development of the chip, package and PCB system board by creating an accurate virtual package model before the designing of a package substrate begins based on the final specification of the integrated chip-package design. Chip-package-system co-design allows optimal cost / performance trade-offs, reduces IC and system development times and improves verification accuracy prior to actual system hardware prototyping. 

Further information about Chip-Package-System (CPS) co-design / co-verification or send your request for information to the ASIC & Foundry team

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