Cortex ^™ M3

• First ARM 32-bit RISC processor based on the new ARMv7-M architecture
• 3-stage pipeline Harvard bus architecture
• 1.25 DMIPS/MHz, due to single cycle multiply and  hardware divide 
• Thumb®-2 instruction set (backward compatible to Thumb ISA)
• Nested Vectored Interrupt Controller NVIC
• Memory Protection Unit MPU
• Embedded Trace Macrocell E™
• Data Watchpoint and Trace unit DWT
• Flash Patch and Breakpoint unit FPB
• Debug Port ( SW-DP or SWJ-DP )
• More details from ARM® Limited – www.arm.com

Features / Services from Toshiba

• Performance tbd
• Flexible and synthesizable memory and core configuration

Benefits

• Enhanced energy efficiency (clock gating, sleep mode)
• Low latency with nested vector interrupt controller (NVIC)
• Thumb-2 backward compatible to Thumb ISA
• 32-bit performance at 8-bit cost

Applications

• Microcontroller, wireless networking with sleep mode, white goods, electronic toys, medical instrumentation

Images courtesy of ARM® Limited - www.arm.com

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